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VHDL COURSE CONTENT

  • Need, Scope, Use and History of VLSI.
  • Introduction to Chip Design Process.
  • Description of Hardware Description Languages
  • VLSI Design Flow
  • Applications of VLSI.

  • Need, Scope, Use and History of VHDL.
  • Applications of VHDL in Market and Industries.
  • Special Features of this Language.
  • Discussion of VHDL & other Languages.

  • Design Process and Steps.
  • Design Simulation
  • Design Synthesis.
  • Design Methodology

              -Top Down

              -Bottom Up


  • Library Declaration
  • Entity
  • Architecture
  • Configuration

  • Variables
  • Constants
  • Signals
  • Delta Delay
  • Operators in VHDL

              -Bottom UpShift Operator

              -Bottom UpRelational Operator

              -Bottom UpArithmetic Operator

  • User-Defined Data Types
  • Pre-Defined Data Types
  • Arrays

  • Keyword description of Dataflow Modeling.
  • When else statement.
  • With Select Statement.

  • Process Keyword.
  • Conditional Statements

              -If else statement

              -Case statement

  • Loops in VHDL

              -UpFor Loop

              -While Loop

              -No Iteration Scheme Loop

  • Sequential Circuits in Behavioral Modeling

              -Flip-Flops

              -Counters

  • Combinational Circuits in Behavioral Modeling

              -Decoder

              -Encoder

              -Multiplexer

              -Logic Gates

  • Attribute

              -Signal Attribute

              -Data Attribute

              -User-Defined Attribute

  • Package

              -Pre-defined Package

              -User-defined Package

  • Sub programs.
  • Function.

              -Local Function

              -Pre-defined Function

  • Procedure.

              -Local Procedure

              -Pre-defined Procedure

  • NULL Statement
  • NEXT Statement
  • EXIT Statement

  • Benefits of Structural Modeling.
  • Components.
  • Component Interfacing
  • Port Mapping

  • Introduction to FINITE STATE MACHINE (FSM).
  • Moore’s Machine.
  • Mealy Machine.
  • Counters (MOD-3, MOD-5, MOD-7)
  • Flip Flops using FSM.

  • SISO
  • PIPO
  • SIPO
  • PISO
  • Memory Design

              -RAM

              -ROM


  • Design of ALU
  • Traffic Light Controller

              -Single way

              -Four way

  • Design of Shift Unit
  • Design of Comparator
  • Booth Multiplier
  • Wallance Tree Multiplier

  • Introduction to FPGA.
  • Introduction to CPLD.
  • Brief Description of Hardware KIT.
  • Working on Physical FPGA & CPLD.
  • Interfacing of LED's.
  • Keypad Scanner

  • MEMORY DESIGN RAM / ROM.
  • CLOCK DIVIDER RTL

  • 7 Segment interfacing.
  • Counter on 7-Segment.
  • LCD Interfacing.

  • Test bench.
  • Delays in VHDL.
  • Generics & generic map.
  • Guarded block.
  • Overloading

              -Operator overloading.

              -Function overloading.


  • Needs of VERILOG HDL & VHDL.
  • Difference between Verilog HDL
  • Application of Verilog HDL
  • Market Need.

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