ASIC & FPGA design methodologies

Training and Internship

Advanced Logic Design

FPGA

Duration :6 weeks
Tool : Xilinx
Digital Design
Combinational Logic
  - Logic Gate
  - Logic gates using Universal Gates
  - Half adder and Full adder gate level
  - Half subtractor and full subtractor gate level
  - HA, FA ,HS, FS using mux
  - Encoder ,decoder
  - MUx and demux
  - Higher mux using lower mux
  - Higher encoder using lower encoder
  - Comparator Multiplier
  - Project 1 on basics of Combinational
  - Sequential logic
  - Latch, FF
  - SR FF, JKFF,DFF,TFF ,Master_Slave_FF
  - Shift Register
  - SISO, PIPO, SIPO,PISO,
Counter :

Asynchrnous counter, Syncrnous counter,up counter, down counter, even counter , Specfic counter, Ring Counter, Johnson counter, Mod 3 counter, Frequency divder f/2,f/3and f/7 FSM : Mealy & Moore ,Sequence detector

Project 2:Design a project relevant with sequential and combinational both.

Note : All Design should be done on Tool as well as Theoretical

FPGA With Verilog

Duration :3 months
Tool : Xilinx
Digital Design
Combinational Logic
  -Logic Gate
  -Logic gates using Universal Gates
  -Half adder and Full adder gate level
  -Half subtractor and full subtractor gate level
  -HA, FA ,HS, FS using mux
  -Encoder ,decoder
  -MUx and demux
  -Higher mux using lower mux
  -Higher encoder using lower encoder
  -Comparator Multiplier
  -Project 1 on basics of Combinational
  -Sequential logic
  -Latch, FF
  -SR FF, JKFF,DFF,TFF ,Master_Slave_FF
  -Shift Register SISO, PIPO, SIPO,PISO
Counter :

Asynchronous counter, Synchronous counter,up counter, down counter, even counter , Specific counter, Ring Counter, Johnson counter, Mod 3 counter, Frequency divder f/2,f/3and f/7 FSM : Mealy & Moore ,Sequence detector

Project 2: Design a project relevant with sequential and combinational both.

Note : All Design should be done on Tool as well as Theoretical

Verilog : All Design of FPGA implement its Verilog code

VLSI Summer Internship Course

Tool : Questasim
Duration : 6 weeks
Advance Digital Design
  -Number systems
  -KMap, Timing diagrams
  -FF
  -latch
  -Counters
  -Various type FF
  -Varous type of Counters
  -RACE condition
  -parity generator
  -priority encoder
  -encoder and decoder
  -mux and demux
  -higher mux using lower mux
  -gate design using mux, Comparator
  -PISO ,SIPO ,clock generation
  -PLL,VCO,Freucy divider
  -Clock multiplication,State machines
  -FSM, mealay and moore, sequence detector
  -CRC calculation logic, Pattern detector

Verilog for Design and Verification :
  -Introduction to Verilog HDL
  -Module,data types,Verilog operators
  -Dataflow modeling,Behavioural modeling
  -gate level modeling, Strucutral modeling
  -Assignment statements, procedural statements
  -always , intial, dealy modeling, system task and function
  -Verilog register, generate, system tasks and function
  -PLI, Design implementation using RTL ,Testbench coding

Projects :
  -Pattern detector
  -Vending Machine, Watchdog timer
  -TL
  -Sychronous FIFO andAsynchronous FIFO,UART Controller, I2C ontroller.

Verilog for Design and Verification

Module-4
Tool : Questasim
Duration : 6 weeks
  -Introduction to Verilog HDL
  -Module,data types
  -Verilog operators
  -Dataflow modeling
  -Behavioural modeling
  -gate level modeling
  -Strucutral modeling
  -Assignment statements
  -procedural
  -vectors,statements
  -always , intial
  -dealy modeling, system task and function
  -Verilog register, generate
  -system tasks and function,PLI
  -Design implementation using RTL
  -Testbench coding Flip flop, counter
  -latch, HA, FA, mux,encoder
  -decoder,CRC generation code

Projects : Pattern detector, Vending Machine, Watchdog timer, TLC,Sychronous FIFO and Asynchronous FIFO,UART Controller, I2C ontroller. Verilog for Verification

All codes verify using Verilog

ASIC Verification Methodologies

SystemVerilog

Tool- Questasim
Duration : 2 months

Study of data types in system Verilog & Implementation of any combinational block using structural modeling & its testbench & verification

  -Basic Constructs Data Types
  -Literals,Strings, User-defined Datatypes
  -Enumerations, structure & union, typedef

Data Types includes : Net type & register type

  -Any one Combinational block i.e. Full Adder
  -Sub-tractor, Gray Code converter etc.

Testbench is having a stimulus generator block for generating input for the combinational block.

  -Study Arrays
  -Dynamic Arrays
  -Associative arrays
  -Queue, Casting 1 Day Data Declarations
  -Operators, Control Statements, Program Block
  -Fork Join

Subroutines n blocking & non blocking statements in Verilog, using some examples.

  -Study Classes
  -Inheritance
  -Polymorphism
  -Encapsulation

Can try an example e.g. we can have half adder in a class & can implement full adder by inheriting half adder class.

  -Ports
  -Interface methods
  -Clocking Block
  - Virtual Interface
  -Coverage, type of bins Randomization, Assertions

Verification IP Development

  -AXI protocol Concept Features signal Timing Diagram
  -AXI VIP Architecture Development
  -AXI Slave model test case development

VLSI Front End Course

Tool - Questasim
Duration- 6 months
Advance Digital Design
  -Number systems
  -KMap
  -Timing diagrams
  -FF,latch,Counters
  -Various type FF,Varous type of Counters
  -RACE condition,parity generator
  -priority encoder, encoder and decoder
  -mux and demux, higher mux using lower mux
  -gate design using mux, Comparator
  -PISO ,SIPO ,clock generation,PLL,VCO
  -Freucy divider, Clock multiplication
  -State machines, FSM, mealay and moore
  -sequence detector,CRC calculation logic, Pattern detector

Verilog for Design and Verification :

  -Introduction to Verilog HDL
  -Module,data types
  -Verilog operators,Dataflow modeling
  -Behavioural modeling,gate level modeling
  -Strucutral modeling, Assignment statements
  -procedural statements
  -always , intial, dealy modeling
  -system task and function,Verilog register
  -generate, system tasks and function,PLI
  -Design implementation using RTL ,Testbench coding

Projects : Pattern detector, Vending Machine

System Verilog

Study of data types in system Verilog & Implementation of any combinational block using structural modeling & its testbench & verification

  -Basic Constructs Data Types
  -Literals,Strings, User-defined Datatypes
  -Enumerations, structure & union, typedef

Data Types includes :

  -Net type & register type
  -Any one Combinational block i.e. Full Adder
  -Sub-tractor, Gray Code converter etc.

Testbench is having a stimulus generator block for generating input for the combinational block.

  -Study Arrays, Dynamic Arrays, Associative arrays
  -Queue, Casting 1 Day Data Declarations, Operators
  -Control Statements, Program Block, Fork Join
  -Subroutines n blocking & non blocking statements in Verilog, using some examples.
  -Study Classes, Inheritance, Polymorphism

Encapsulation half adder in a class & can implement full adder by inheriting half adder class

  -Ports, Interface methods
  -Clocking Block, Virtual Interface
  -Coverage, type of bins Randomization, Assertions

Module-7 VLSI Front End Verification Course

Duration : 6 months
Tool : Questasim
Advance Digital Design
  -Number systems
  -KMap, Timing diagrams
  -FF,latch,Counters,Various type FF

Various type of Counters

  -RACE condition
  -parity generator , priority encoder
  -encoder and decoder, mux and demux
  -higher mux using lower mux, gate design using mux
  -Comparator, PISO ,SIPO ,clock generation,PLL,VCO
  -Freucy divider, Clock multiplication,State machines
  -FSM, mealay and moore, sequence detector,CRC calculation logic
  -Pattern detector

Verilog for Design and Verification :

  -Introduction to Verilog HDL
  -Module,data types
  -Verilog operators
  -Dataflow modeling
  -Behavioural modeling
  -gate level modeling, Strucutral modeling
  -Assignment statements, procedural statements
  -always , intial, dealy modeling
  -system task and function,Verilog register
  -generate, system tasks and function
  -PLI, Design implementation using RTL ,Testbench coding

Projects : Pattern detector, Vending Machine

System Verilog

Study of data types in system Verilog & Implementation of any combinational block using structural modeling & its testbench & verification.

  -Basic Constructs Data Types
  -Literals,Strings, User-defined Datatypes
  -Enumerations, structure & union, typedef

Data Types includes : Net type & register type.

  -Any one Combinational block i.e. Full Adder
  -Sub-tractor, Gray Code converter etc.

Testbench is having a stimulus generator block for generating input for the combinational block.

  -Study Arrays, Dynamic Arrays
  -Associative arrays, Queue
  -Casting 1 Day Data Declarations
  -Operators, Control Statements
  -Program Block, Fork Join
  -Subroutines n blocking & non blocking statements in Verilog, using some examples
  -Study Classes
  -Inheritance, Polymorphism

Encapsulation half adder in a class & can implement full adder by inheriting half adder class.

  -Ports, Interface methode
  -Clocking Block, Virtual Interface
  - Coverage, type of bins Randomization, Assertions

Verification IP Development

  -AXI / APB protocol Concept Features signal Timing Diagram
  -AXI VIP Architecture Development
  -AXI Slave model test case development

Assertion Based Verification: SVA

UVM

Three Mini Projects

Industry Standard Project

Scripting Language: Perl

Operating System - Linux

EDA Tools : Mentor Graphics - Questa, Modelsim SE and DE

Xilinx - ISE

Digital design
  - combinational circuits
  - sequential
  - state machines
  - Advanced Design Issues
             - Metastability
             - Noise margins
             - Power
             - Fan-out
             - Design rules
             - Skew
             - Timing considerations

Computer architecture
             - computer architecture
             - Peripheral
             - Ethernet
             - PCI
             - USB

Verilog
             - RTL modelling
             - Testbench modeling

HDL
             - The concept of Simulation
             - HDL Simulation and Modeling
             - The Synthesis Concept
             - Synthesis of high level constructs
             - Timing Analysis of Logic Circuits
             - Combinatorial Logic Synthesis
             - State Machine Synthesis
             - Efficient Coding Styles

Verification
             - Basic concept of verification
             - Test bench architecture
             - UVM

Layout

Circuit Design